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K3P7V(U)1000B-YC
64M-Bit (8Mx8 /4Mx16) CMOS MASK ROM
FEATURES
* Switchable organization 8,388,608 x 8(byte mode) 4,194,304 x 16(word mode) * Fast access time Random Access Time/Page Access Time 3.3V Operation : 100/30ns(Max.)@CL=50pF, 120/40ns(Max.)@CL=100pF 3.0V Operation : 120/40ns(Max.)@CL=100pF 8 Words / 16 Bytes page access * Supply voltage : single +3.0V/ single +3.3V * Current consumption Operating : 60mA(Max.) Standby : 50A(Max.) * Fully static operation * All inputs and outputs TTL compatible * Three state outputs * Package K3P7V(U)1000B-YC : 48-TSOP1-1218
CMOS MASK ROM
GENERAL DESCRIPTION
The K3P7V(U)1000B-YC is a fully static mask programmable ROM fabricated using silicon gate CMOS process technology, and is organized either as 8,388,608 x 8 bit(byte mode) or as 4,194,304 x 16 bit(word mode) depending on BHE voltage level.(See mode selection table) This device includes page read mode function, page read mode allows 8 words (or 16 bytes) of data to read fast in the same page, CE and A3 ~ A21 should not be changed. This device operates with 3.0V or 3.3V power supply, and all inputs and outputs are TTL compatible. Because of its asynchronous operation, it requires no external clock assuring extremely easy operation. It is suitable for use in program memory of microprocessor, and data memory, character generator. The K3P7V(U)1000B-YC is packaged in a 48-TSOP1.
FUNCTIONAL BLOCK DIAGRAM
Pin Name A21 . . . . . . . . A3 A0~A2 A-1 X BUFFERS AND DECODER MEMORY CELL MATRIX (4,194,304x16/ 8,388,608x8) Q15 /A-1 BHE SENSE AMP. DATA OUT BUFFERS ... CE OE BHE CONTROL LOGIC Q0/Q8 Q7/Q15 CE OE VCC Vss N.C A0 - A2 A3 - A21 Q0 - Q14 Pin Function Page Address Inputs Address Inputs Data Outputs Output 15(Word mode)/ LSB Address(Byte mode) Word/Byte selection Chip Enable Output Enable Power Ground No Connection
Y BUFFERS AND DECODER
K3P7V(U)1000B-YC
PIN CONFIGURATION
CMOS MASK ROM
BHE A16 A15 A14 A13 A12 A11 A10 A9 A8 A19 A21 A20 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
TSOP1
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
VSS VSS Q15/A-1 Q7 Q14 Q6 Q13 Q5 Q12 Q4 VCC VCC N.C Q11 Q3 Q10 Q2 Q9 Q1 Q8 Q0 OE VSS VSS
K3P7V(U)1000B-YC
ABSOLUTE MAXIMUM RATINGS
Item Voltage on Any Pin Relative to VSS Temperature Under Bias Storage Temperature Symbol VIN TBIAS TSTG Rating -0.3 to +4.5 -10 to +85 -55 to +150 Unit V C C
NOTE : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
RECOMMENDED OPERATING CONDITIONS(Voltage reference to VSS, TA=0 to 70C)
Item Supply Voltage Supply Voltage Symbol VCC VSS Min 2.7/3.0 0 Typ 3.0/3.3 0 Max 3.3/3.6 0 Unit V V
DC CHARACTERISTICS
Parameter Operating Current Standby Current(TTL) Standby Current(CMOS) Input Leakage Current Output Leakage Current Input High Voltage, All Inputs Input Low Voltage, All Inputs Output High Voltage Level Output Low Voltage Level Symbol ICC ISB1 ISB2 ILI ILO VIH VIL VOH VOL IOH=-400A IOL=2.1mA Test Conditions Cycle=5MHZ, all outputs open, CE=OE=VIL, VIN=0.45V to 2.4V (AC Test Condition) CE=VIH, all outputs open CE=VCC, all outputs open VIN=0 to VCC VOUT=0 to VCC 2.0 -0.3 2.4 VCC=3.3V0.3V VCC=3.0V0.3V Min Max 60 50 500 50 10 10 VCC+0.3 0.6 0.4 Unit mA mA A A A A V V V V
NOTE : Minimum DC Voltage(VIL) is -0.3V an input pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input pins(VIH) is VCC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.
K3P7V(U)1000B-YC
MODE SELECTION
CE H L L OE X H L BHE X X H L Q15/A-1 X X Output Input Mode Standby Operating Operating Operating
CMOS MASK ROM
Data High-Z High-Z Q0~Q15 : Dout Q0~Q7 : Dout Q8~Q14 : Hi-Z Power Standby Active Active Active
CAPACITANCE(TA=25C, f=1.0MHz)
Item Output Capacitance Input Capacitance Symbol COUT CIN Test Conditions VOUT=0V VIN=0V Min Max 12 12 Unit pF pF
NOTE : Capacitance is periodically sampled and not 100% tested.
AC CHARACTERISTICS(TA=0C to +70C,VCC=3.3V/3.0V0.3V, unless otherwise noted.)
TEST CONDITIONS
Item Input Pulse Levels Input Rise and Fall Times Input and Output timing Levels Output Loads Value 0.45V to 2.4V 10ns 1.5V 1 TTL Gate and CL=50pF or 100pF
READ CYCLE
Item Read Cycle Time Chip Enable Access Time Address Access Time Page Address Access Time Output Enable Access Time Output or Chip Disable to Output High-Z Output Hold from Address Change
NOTE : Page Address is determined as below. Word mode (BHE=VIH) : A0, A1, A2 Byte mode (BHE=VIL) : A-1, A0, A1, A2
Symbol tRC tACE tAA tPA tOE tDF tOH
K3P7V1000B-YC10 (CL=50pF) Min 100 100 100 30 30 20 0 Max
K3P7V1000B-YC12 (CL=100pF) Min 120 120 120 40 40 20 0 Max
K3P7U1000B-YC12 (CL=100pF) Min 120 120 120 40 40 20 0 Max
Unit ns ns ns ns ns ns ns
K3P7V(U)1000B-YC
TIMING DIAGRAM
READ
ADD A0~A21 A-1(*1) tACE CE tOE OE tOH DOUT D0~D7 D8~D15(*2) VALID DATA tAA
CMOS MASK ROM
ADD1 tRC
ADD2 tDF(*3)
VALID DATA
PAGE READ
CE
tDF(*3)
OE
ADD A0,A1,A2 A -1(*1) tAA DOUT D0~D7 D8~D15(*2)
1 st tPA VALID DATA
2 nd
3 rd
VALID DATA VALID DATA VALID DATA
NOTES : *1.Byte Mode only. A-1 is Least Significant Bit Address.(BHE = VIL) *2. Word Mode only.(BHE = VIH) *3. tDF is defined as the time at which the outputs achieve the open circuit condition and is not referenced to VOH or VOL level.

ADD A3~A21

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